MIT researchers developed a new method that allows the layers of interconnect patterns to "self-assemble" into much finer pattern lines. This new method should make it more cost-effective to go below the 10nm process node, compared to EUV lithography.
from Tom's Hardware http://ift.tt/2nfS1PQ
via IFTTT
Home / IFTTT /
Tech /
Tom's Hardware /
TomsHardware
/ MIT Researchers Reveal More Efficient Way To Build Chips Below The 10nm Process
- Blogger Comment
- Facebook Comment
Subscribe to:
Post Comments
(
Atom
)
0 comments:
Post a Comment