In what seems to be a major blunder by the SiPearl PR team, a recent visit by a local French politician resulted in the public Twitter posting in what looks like the floor plan of the company’s first-generation server chip project “Rhea”.
During a visit of Alexandra Dublanche, a local ÃŽle-de-France politician and vice president of economic development and other responsibilities for the region, the PR teams had made some photo-op captures of a tour of the office. Amongst the published pictures includes a shot of the company’s Rhea server chip project with some new, until now unreleased details of the European Processor Initiative-backed project.
Accélérer le développement européen de microprocesseurs à haute performance est un enjeu de souveraineté 🇪🇺
— Alexandra Dublanche (@ADublanche) September 8, 2020
C’est le défi auquel s’attaque la pépite technologique @SIPEARL_SAS basée à #MaisonsLaffitte en @iledefrance
La Région sera à ses côtés face à cet enjeu majeur! pic.twitter.com/kcBwghlfsP
In a close-up and up-scaling of the image, we can see that it’s a detailed floor-plan of the server SoC Rhea, labelled for a target TSMC 7nm process.
We can detail 72 CPU cores and 68 mesh network L3 cache slices in the floor plan, surrounded by various IP whose labels are too small to be legible. SiPearl had previously confirmed that the project uses Arm’s upcoming Neoverse “Zeus” cores which succeed the Neoverse N1 Ares cores that are being used in current generation Arm server SoC designs such as Amazon’s Graviton2 or Ampere’s Altra.
Beyond the confirmation of a core-count, we also see that the Rhea design sports a high-end memory subsystem, with the floor plan labelled as having 4x HBM2E controllers and 4-6 DDR5 controllers. Such a hybrid memory system would allow for extremely high bandwidth to be able to feed such a large number of cores, while still falling back to regular DIMMs to be able to scale in memory capacity.
The Rhea family of processors is roadmapped to come to market in 2021. The only curious divergence here is that SiPearl previously stated that this was an N6 project, whilst the recent Twitter picture states it being N7. Given that both processes are design compatible, it might just be a recent shift in the project, or the company still plans to productise it in the N6 node when it comes to market.
The design’s aggressive memory subsystem with the inclusion of HBM2E points out that the company is aiming for quite high performance targets, joining the ranks of Fujitsu in terms of designing a CPU with advanced HBM memory.
Related Reading:
- European Processor Initiative Backed SiPearl Announces Licensing of Arm Zeus Neoverse CPU IP
- Amazon's Arm-based Graviton2 Against AMD and Intel: Comparing Cloud Compute
- Next Generation Arm Server: Ampere’s Altra 80-core N1 SoC for Hyperscalers against Rome and Xeon
- Ampere’s Product List: 80 Cores, up to 3.3 GHz at 250 W; 128 Core in Q4
- A Success on Arm for HPC: We Found a Fujitsu A64FX Wafer
- New #1 Supercomputer: Fugaku in Japan, with A64FX, take Arm to the Top with 415 PetaFLOPs
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